1. Field of the Invention
The present invention relates generally to solid state imaging devices and, more particularly, is directed to a solid state imaging device of a so-called all pixel read out type.
2. Description of the Prior Art
Conventional CCD (charge-coupled device) solid state imaging devices include two horizontal transfer registers, for example, in order to improve a resolution. Signal charges of odd-numbered lines and signal charges of even-numbered lines are simultaneously transferred by the two separate horizontal transfer registers and signal charges of two lines are read out during 1H (H is a horizontal scanning period) to thereby read out full pixels.
In order to increase the amount of signal charges that the horizontal transfer register can handle sufficiently, the channel width of the horizontal transfer register must be increased in accordance therewith.
The reason for this is that, when an amplitude of a horizontal transfer clock is made constant, the amount of signal charge handled by the horizontal transfer register is proportional to the area of the horizontal transfer register per bit so that the amount of signal charges handled by the horizontal transfer register can be increased by increasing the channel length and channel width of the horizontal transfer register per bit. In this case, however, the channel length of the horizontal transfer register per bit is restricted by the dimensions of an image section so that only the channel width of the horizontal transfer register is allowed to be increased.
However, if the channel width of the horizontal transfer register is increased, then intensity of electric field produced in the horizontal transfer register is decreased by the horizontal transfer clock applied to the transfer electrode. The intensity of electric field is decreased particularly at the central portion of the horizontal transfer register in the channel width direction.
As the intensity of the transfer electric field is decreased, a transfer rate of signal charge in the vertical direction of the horizontal transfer register is lowered. Consequently, it is frequently observed that a part of signal charges cannot be transferred.
Therefore, in the conventional CCD solid state imaging device of all pixel read out type, when signal charges of one line are parallelly transferred from the register at the image section side to the register at the opposite side of the two horizontal transfer registers, the signal charges cannot be transferred completely. There is then the risk that an image quality is deteriorated.
The assignee of the present application has previously proposed a CCD solid state imaging device of all pixel read out type in which a horizontal transfer register at the image section side is formed of transfer sections of a plurality of stages (e.g., two stages) and signal charge of the same pixel is horizontally transferred by these transfer sections individually in order to increase the amount of signal charges by the horizontal transfer registers without lowering the transfer rate in the horizontal transfer register (see Japanese laid-open patent publication No. 3-72790).
A schematic structure and operation of such previously-proposed CCD solid state imaging device will be described below.
FIG. 1 of the accompanying drawings shows a structure of the conventional CCD solid state imaging device. As shown in FIG. 1, a CCD image sensor section 3 of an interline transfer type comprises a plurality of photo-sensors 1 arrayed at the unit of pixel in a two-dimensional fashion and a plurality of vertical transfer registers 2 disposed at every vertical column of these photo-sensors 1 to vertically transfer signal charges generated by the photo-sensors 1.
A first horizontal transfer register 4 is disposed under the image section 3. The first horizontal transfer register 4 comprises two transfer sections 4a, 4b that simultaneously transfer a signal charge of one line in the horizontal direction in a divided fashion. These transfer sections 4a, 4b are substantially the same in channel width. The transfer sections 4a, 4b are spaced apart a little and arranged in parallel to each other and unitarily formed as one body in an output section. A sum of channel widths of the transfer sections 4a, 4b becomes the channel width of the first horizontal transfer register 4. The value of this channel width of the first horizontal transfer register 4 is set sufficient so that the amount of signal charges handled by the first horizontal transfer register 4 can be increased sufficiently.
In the first horizontal transfer register 4, a control gate section 5 is disposed between the two transfer sections 4a, 4b. A signal charge of the same pixel is distributed to transfer sections 4a, 4b under the control of the control gate section 5.
Under the first horizontal transfer register 4 is disposed parallelly a second horizontal transfer register 6 with a small distance from the first horizontal transfer register 4. The channel width of the second horizontal transfer register 6 is set to be substantially the same as that of the first horizontal transfer register 4.
A transfer gate section 7 is disposed between the first and second horizontal transfer registers 4 and 6. Under the control of the transfer gate section 7, the signal charge of one line that was transferred from the vertical transfer registers 1 to the first horizontal transfer register 4 is further transferred to the second horizontal transfer register 6.
The signal charges horizontally transferred by the first and second horizontal transfer registers 4, 6 are converted by output sections 8.sub.1, 8.sub.2 into signal voltages and then developed as outputs OUT1, OUT2, respectively.
Since the first horizontal transfer register 4 is formed of the transfer sections 4a, 4b of a plurality of stages (two stages in this example) as described above, the channel widths of the respective transfer sections 4a, 4b are narrow although the channel width of the first horizontal transfer register 4 is large on the whole. Thus, intensity of transfer electric field can be prevented from being lowered, and a transfer rate with which the signal charge is transferred through the first horizontal transfer register 4 to the second horizontal transfer register 6 can be avoided from being lowered.
In other words, the amount of signal charges handled by the first horizontal transfer register 4 can be increased without lowering the transfer rate in the first horizontal transfer register 4.
In the first horizontal transfer register 4, signal charges that had been separately transferred by the transfer sections 4a, 4b in the horizontal direction are joined together again in the output section 8.sub.1 so that the amount of signals charges handled by the first horizontal transfer register 4 per bit is constant regardless of the amounts of signal charges respectively transferred by the two transfer sections 4a, 4b.
The amounts of signal charges that the two transfer sections 4a, 4b handle per bit are determined by the channel length and channel width of one bit. Therefore, when signal charges are distributed by the two transfer sections 4a, 4b, if the amount of signal charges distributed to one transfer section exceeds the amount of signal charges that the transfer section can handle, then all signal charges of one pixel cannot be transferred completely although the amount of signal charges handled by the first horizontal transfer register 4 is increased.
Therefore, when signal charges are distributed between the two transfer sections 4a, 4b, signal charges must be distributed between the two transfer sections 4a, 4b in consideration of the amounts of signal charges handled by each of the two transfer sections 4a, 4b.